In order to achieve a high speed switching in the bipolar transistor, it is necessary to improve the maximum oscillating frequency (hereinafter abbreviated as f.sub.max) which is one of the characteristics of the transistor. The value of f.sub.max is given according to the following formula: EQU f.sub.max =[f.sub.T /(8.pi.R.sub.B C.sub.BC)].sup.0.5
Here, f.sub.T denotes cut-off frequency, R.sub.B base resistance, and C.sub.BC base-collector capacitance. In order to improve f.sub.max, as obvious from the foregoing formula, it is necessary to make the cut-off frequency f.sub.T higher, make the base-collector capacitance C.sub.BC smaller and to reduce the base resistance R.sub.B.
Conventionally, in order to improve the cut-off frequency f.sub.T, the depth of the junction, in particular the depth of base layer, taken in the longitudinal direction has been made shallower by reconsidering the heat treatment and ion implantation conditions.
Further, in order to reduce a base-collector capacitance and the base resistance, as shown in FIG. 1, the device dimension taken in the horizontal direction has been reduced by utilizing a self-aligning aligning type structure which comprises an emitter diffusion layer 12 formed in self-aligning manner relative to a base electrode comprising a polycrystalline silicon layer 6A. Incidentally, in the same figure, reference numeral 1 denotes a silicon substrate, 2 a buried layer, 3 an epitaxial layer, 4 a field oxide film, 10 a silicon oxide film, 10A a side wall comprising a silicon oxide film, 12 an emitter diffusion layer, 8a base diffusion layer, 5 a collector diffusion layer, 7 an external base diffusion layer, 11 a highly doped N.sup.+ -type polycrystalline silicon layer, and 6A a highly doped P.sup.+ -type polycrystalline silicon layer.
In recent years, in order to improve f.sub.max of the bipolar transistor, a further reduction of the base resistance becomes necessary, and it has been proposed to use a silicide or polycide for the base electrode. However, if a high temperature heat treatment is conducted with a silicide layer made of, for example, tungsten silicide contacting the polycrystalline silicon layer containing highly doped boron, then boron within the polycrystalline silicon layer diffuses into the silicide layer, and the boron concentration within the polycrystalline silicon layer in the neighborhood of the interface between the silicide layer and the polycrystalline silicon layer is decreased. As a result, junction between the silicide layer and the polycrystalline silicon layer results in a Schottky junction and the contact resistance is increased. This is also the case with the gate electrode of the MOSFET.
In order to solve the foregoing problems, a method has been proposed in which boron is introduced with a high concentration by ion implantation process or the like into not only the polycrystalline silicon layer, which is the lower layer, but also into the silicide layer, which is the upper layer, so that the diffusion of the boron within the polycrystalline silicon layer into the silicide layer is suppressed even if heat treatment is conducted. However, in this method, if the heat treatment temperature is above 850 degrees Centigrade and the treatment time is prolonged over, for example, 30 min and above, then the contact resistance is increased, and the method can be applied only under the limited manufacturing conditions.
Further, other than the foregoing ion implantation process, as described in Japanese Patent Application Laid-Open No. 4-150037, a method of forming a silicon oxide film (BSG) containing boron on the surface of the silicide layer at the low temperature of about 450 degrees Centigrade is also proposed.
Further, as described in International Electron Devices Meeting, pp 845 through 848, 1992, by T. Fujii, a method has been also proposed in which, after the polycrystalline silicon layer is formed on the surface of the silicide layer, a silicon oxide film is formed on the polycrystalline silicon layer to prevent boron contained within the lower polycrystalline silicon layer from diffusing into the silicide layer in the subsequent heat treatment process for redistribution. This is based on the following reasons.
That is, segregation of boron at the interface between the oxide film and the tungsten silicide layer is caused because the B-0 phase is ready to form at the interface. Therefore, if, instead of forming the oxide film on the tungsten silicide layer directly, the polycrystalline silicon layer is inserted between both of them, then formation of the B-0 phase is suppressed, sucking out of the boron from the polycrystalline silicon layer below the tungsten silicide layer becomes small, and the boron concentration at the interface between the tungsten silicide layer and the polycrystalline silicon layer can be maintained high. It is hereinafter described with reference to FIGS. 2A through 2C.
First, as shown in FIG. 2A, an N.sup.+ -type buried layer 2 and an N-type epitaxial layer 3 are sequentially formed on a P-type silicon substrate 1.
Next, a field oxide film 4 having a thickness of 300 through 600 nm is selectively formed. By utilizing the ion implantation process, a collector diffusion layer 5 is formed so as to reach the N.sup.+ -type buried layer 2. Next,, after the oxide film lying on an active base area is removed according to the photoetching process, a 100 through 300 nm thick P.sup.+ -type polycrystalline silicon layer 6 containing boron is grown. Introduction of boron into the polycrystalline silicon layer is conducted according to, for example, the ion implantation process under the implantation conditions of energy of 5 through 10 KeV and 5.times.10.sup.15 through 1.times.10.sup.16 cm.sup.-2. Incidentally, boron may be introduced while the polycrystalline silicon layer is being formed.
Next, a metallic silicide layer, for example a tungsten silicide layer 13, is formed to a thickness of 100 to 200 nm by utilizing a known sputtering process. Incidentally, boron may be introduced into the tungsten silicide layer 13 by utilizing the ion implantation process. Next, the polycrystalline silicon layer 14A is formed to a thickness of 20 to 80 nm. Next, a silicon oxide film 10 is formed to a thickness of 100 to 200 nm by utilizing the LPCVD process. Next, these are patterned to a predetermined form to form a base lead electrode comprising polycrystalline silicon layers 6, 14A and tungsten silicide layer 13. Next, a polycrystalline silicon layer 14B is grown to a thickness of 20 to 80 nm. Next, the surface of the substrate is dry etched to leave the polycrystalline silicon layer 14B on the lateral surface of the base lead electrode, as shown in FIG. 2B.
Next, as shown in FIG. 2C, boron ions are implanted into the active base area under the condition of 10 keV and 5.times.10.sup.13 cm.sup.-2 to form a base diffusion layer 8. Next, a side wall 10A comprising a silicon oxide film having a thickness of 100 to 300 nm is formed on the lateral surface of the base lead electrode according to a known technique. As a result, the tungsten polycide base lead electrode is covered in its upper and lateral surfaces with the oxide film.
Next, an N.sup.+ -type polycrystalline silicon layer 11 containing an N-type impurity, for example arsenic, is deposited to a thickness of 200 to 300 nm to form an emitter lead electrode. Next, an emitter diffusion layer 12 is formed by heat treatment in the atmosphere of nitrogen at 900 to 950 degrees Centigrade for 10 min. Thereafter, although not shown, an interlayer insulating film and electrodes are formed as well known to complete a bipolar transistor.
In the foregoing method of forming the silicon oxide film (BSG) containing the boron on the surface of the silicide layer, in order to prevent occurrence of the increase of contact resistance between the silicide layer and the polycrystalline silicon layer by heat treatment, the boron concentration of at least 10 mol % is necessary within BSG film. However, if the BSG film of this concentration is applied to the surface of the silicide layer, then the boron within the BSG film is diffused into the polycrystalline silicon layer 11 adapted for forming the emitter due to the heat treatment in the subsequent process such as an emitter forming process, and the increase of the emitter resistance or an insufficient emitter junction result.
On the other hand, when the foregoing method in which the polycrystalline silicon layer and the silicon oxide film are formed on the silicide layer as shown in FIGS. 2A to 2C, if the bipolar transistor is formed, the following problems arise.
If the tungsten polycide electrode is used to the base lead electrode of the bipolar transistor, in order to suppress the segregation of boron at the interface of the sidewall 10A, it is necessary to provide the polycrystalline silicon layer 14B not only on the upper surface of the electrode but also on the lateral surface of the electrode. However, this not only incurs the increase of the manufacturing process, but also, as obvious from the cross-sectional view of FIG. 2C, the distance between the polycrystalline silicon layer 14B on the lateral surface of the base electrode and the polycrystalline silicon layer 11 of the emitter electrode come near and, as shown by arrow X, both electrodes become easy to short causing a great reduction of the yield. Further, since the polycrystalline silicon film is left on the lateral surface of the base electrode, as shown in FIGS. 2A and 2B, after the polycrystalline silicon layer 14B is grown, the entire surface thereof is etched back by dry etching. At this time, since the selection ratio of the etching between the polycrystalline silicon layer 14B and the silicon substrate is nearly equal to 1, etching cannot be stopped at the interface between the polycrystalline silicon layer 14B and the epitaxial layer 3, reaching up to the latter 3. As a result, defects are introduced into the silicon substrate at the emitter forming area, causing junction leakage, or as shown by arrow Y, if the amount by which the silicon substrate is dug is great, then a link base area below the sidewall 10A is not sufficiently formed, and the base resistance is increased to degrade the high speed switching characteristic of the transistor greatly.